This invention relates to a clock control circuit and to a clock control method.
An arrangement using a DLL (Delayed-Locked Loop) of the kind shown in FIG. 18 is known as a circuit that generates a signal having a prescribed phase with respect to an input signal. With regard to the arrangement shown in FIG. 18, see Reference 1 (ISSCC 1997 pp. 332-333, S. Sidiropoulos and Mark Horowitz et al., xe2x80x9cA Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400 MHz Operating Rangexe2x80x9d).
As shown in FIG. 18, the DLL has an input buffer 11, a voltage-controlled delay line 14, a phase comparator 12 for detecting a phase difference between an output signal of the voltage-controlled delay line 14 and an output signal of the input buffer 11, and a filter 13 for smoothing a phase-difference detection signal output from the phase comparator 12. The voltage-controlled delay line 14 comprises a plurality of cascade-connected buffers. The phase comparator 12 is constituted by, e.g., a D-type flip-flop. The voltage-controlled delay line 14 is supplied with a voltage obtained by integrating the output signal of the phase comparator 12 by the filter 13, which includes a charge pump and an RC filter for converting the output signal of the phase comparator 12 to a voltage signal. The delay time in the voltage-controlled delay line 14 is variably set and feedback control is performed in such a manner that the phase of the output of input buffer 11 and the phase of the output of voltage-controlled delay line 14 will coincide (i.e., so that the phase difference between them will become zero). The multiple buffers of the voltage-controlled delay line 14 produce output clocks of equally spaced phase differences.
FIG. 19 illustrates a clock control circuit that produces a multiphase clock by replacing the voltage-controlled delay line 14 of FIG. 18 with a variable oscillator circuit 15 such as a VCO (Voltage-Controlled Oscillator). With regard to the arrangement shown in FIG. 19, see Reference 2 (ISSC 1993 pp. 160-161, Mark Horowitz et al., xe2x80x9cPLL Design for a 500 MB/s Interfacexe2x80x9d). FIG. 19 schematically illustrates one part of the main loop of a PLL circuit described in Reference 2. The variable oscillator circuit 15 such as a VCO produces a plurality of clock outputs (e.g., a plurality of clock outputs of equally spaced phase differences) and supplies these to transmit and receive fine loops (not shown) so that the phase of the internal clocks undergoes fine adjustment.
The arrangements shown in FIGS. 18 and 19 have a feedback loop constituted by a DLL or PLL and exhibit phase jitter ascribable to the feedback loop. This makes it difficult to generate correctly a signal of a desired phase. The present invention has been devised in view this problem.
Accordingly, it is an object of the present invention to provide a clock control circuit and method for precisely generating output clocks of a desired phase difference with respect to an input clock.
In accordance with one aspect of the present invention, the foregoing object is attained by providing a clock control circuit comprising: a multiphase clock generating circuit for generating and outputting a plurality of clocks, phases of which differ from one another (termed xe2x80x9cmultiphase clocksxe2x80x9d), a selector circuit, receiving a plurality of clocks output from said multiphase clock generating circuit, for selecting as an output signal one of the clocks received; a phase comparator circuit for detecting and outputting a phase difference between an output signal obtained by delaying the output signal of said selector circuit through a first variable delay circuit and one of the clocks output from said multiphase clock generating circuit; a filter for smoothing a phase difference detection signal output from said phase comparator circuit, an output signal of said filter being used for varying a delay time of said first variable delay circuit; and a second variable delay circuit, a delay time thereof varied by the output signal of said filter, wherein a signal obtained by delaying the input clock signal through said second variable delay circuit is delivered as an output clock.
A clock control circuit in accordance with another aspect of the present invention, comprises: a phase-difference generating circuit for outputting a signal obtained by delaying an input clock by a predetermined phase difference on the basis of phase decision information applied thereto; a first variable delay circuit for delaying an output of the phase-difference generating circuit; a phase comparator circuit for detecting a phase difference between the output of the phase-difference generating circuit and an output signal from the first variable delay circuit; and a filter for smoothing the phase-difference detection signal output from the phase comparator circuit; the first variable delay circuit having its delay time varied by the output of the filter, and the clock control circuit further comprising a second variable delay circuit having its delay time varied by the output of the filter; wherein a signal obtained by delaying the input clock by the second variable delay circuit is delivered as an output clock.
A clock control circuit in accordance with another aspect of the present invention, comprises: a phase-difference generating circuit, to which an input clock and an output clock are input, for producing first and second output signals, which have a phase difference between them decided by entered phase decision information, based upon the input clock and the output clock; a first variable delay circuit for delaying the second output signal of the phase-difference generating circuit; a phase comparator circuit for detecting and outputting the phase difference between the first and second output signals output from the phase-difference generating circuit; and a filter for smoothing the phase-difference detection signal output from the phase comparator circuit; the first variable delay circuit having its delay time varied by the output of the filter, and the clock control circuit further comprising a second variable delay circuit having its delay time varied by the output of the filter; wherein signals obtained by delaying the input clock by each of the first and second variable delay circuits are delivered as first and second output clocks, and the first output clock enters the phase-difference generating circuit as the output clock.
A clock control method in accordance with further aspect of the present invention comprises the following steps:
step 1: generating, by a multiphase clock generating circuit that has received an input clock signal from an input buffer, a plurality of clocks, the phases of which differ from one another, from the input clock signal;
step 2: selecting one of the clocks from said multiphase clock generating circuit by a selector circuit;
step 3: delaying the selected clock by a first variable delay circuit;
step 4: detecting, by a phase comparator circuit, a phase difference between an output signal of a clock buffer receiving an output signal from said first variable delay circuit and one of the clocks output from said multiphase clock generating circuit, and variably adjusting a delay time of said first variable delay circuit on the basis of a signal obtained by smoothing the result of the phase comparison by a filter; and
step 5: producing an output clock signal, having a desired phase relationship with respect to the input clock signal, from a clock buffer that receives an output signal from a second variable delay circuit, to which an output signal of said input buffer is fed and which has a delay time varied by the output signal of said filter.
A clock control method in accordance with further aspect of the present invention comprises the following steps:
step 1: supplying an output signal of an input buffer, which receives an entered clock, to a phase-difference generating circuit;
step 2: generating, by said phase-difference generating circuit, a signal obtained by delaying an output signal of said input buffer by a predetermined phase difference on the basis of phase decision information applied thereto;
step 3: detecting, by a phase comparator circuit, a phase difference between an output of a clock buffer dummy, which receives as an input an output signal from a first variable delay circuit that delays an output signal of said phase-difference generating circuit, and the output signal of said phase-difference generating circuit;
step 4: smoothing a result of the phase comparison by a filter and varying delay time of said first variable delay circuit by an output signal from said filter; and
step 5: producing an output clock signal from a clock buffer which receives as an input an output signal from a second variable delay circuit which receives an output signal of said input buffer and which has its delay time varied by the output of said input buffer.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.